Názor k článku Máme parametry a takty Exynosu 2200 s grafikou Radeon. Má Cortex-X2 s ARMv9 a SVE2 od del42sa - "Čip bude 4nm (zatímco Exynos 2100 je 5nm)"...

"Čip bude 4nm (zatímco Exynos 2100 je 5nm)"

není ten "4nm" přejmenovaný původní 5nm LPP s vyšší densitou ?

At a high level, the 5LPE node is really an extension of the company 7-nanometer process and is planned as a 2nd generation EUV process, building on the learning from 7LPP. To that end, 5LPE uses the same 7LPP transistors, SRAM and offers GR compatibility.

Samsung™s last FinFET node will be the 4LPE node. 4LPE is similar to 5LPE but shrinks the M1 pitch from 40 nm to 28 nm and the M3 from 36 nm to 32 nm. We have also heard that the fin pitch is planned to be reduced to 25 nm but we could not formally confirm it. With the few numbers we currently have, we have estimated 4LPE to have a cell-level transistor density of 137 MTr/mm². Planned for around 2021, this will be the least dense process compared to both TSMC N5 and Intel™s 7 nm nodes.

4nm process

We can follow up on the news that the newly emerging 4LPE process is in fact a renamed 5LPA process. From the current Samsung roadmap, it really looks like that. The report was created as a logical construction based on the fact that Samsung introduced a process called 4LPE, which, however, has exactly the same parameters as the originally introduced 5LPA.

https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/